Flash memory devices such as NAND flash memory devices are built with rows of floating transistors. In single level cells (SLC) devices each transistor row is called page and can be programmed separately. SLC cells store a single bit of information per cell. In multiple level cells (MLC) devices each transistor holds several levels (multiple bits of information per cell), effectively each MLC flash row contains several pages. E.g. most significant bit (MSB) and Least significant bit (LSB) for 2 bit per cell flash devices, MSB, central significant bit (CSB) and LSB for 3 bit per cell.
A flash memory device, once programmed with data, may contain errors that may be present immediately or may be accumulated over the time. The amount of errors depends on many factors, including number of Program-Erase cycles page has undergone, time passed from programming moment, temperature and page physical properties.
In order to protect programmed data Error Correcting Codes (ECC) are used. Additionally to ECC other techniques may be used. E.g. DSP, data interleaving between several pages, etc.
Flash memory device rows may differ in their properties according to their physical location within flash memory block. In MLC flash devices different pages in a row (i.e. MSB, LSB) can have different properties too. There may be also difference in number of errors due to program coupling between pages, also called even and odd pages.
The reliability of a flash memory device depends on the reliability of all its components. The component with lowest reliability will define the reliability of entire system. In case on flash memory devices, pages with lowest reliability will define the reliability of entire system.
In order to get maximal reliability of the entire system, ECC code should fit page's quality. In a high quality page (i.e. less errors) a more relaxed ECC code can be used. In a lower quality page (i.e. more errors) a stronger ECC code can be used. Usually different ECC codes means different amount (or code rate) of code redundancy vs. payload data. Stronger code means more redundancy means lower code rate.
It is noted that the ECC may include applying a stronger ECC code than required. In such case lower code rate is got, more flash memory is used for redundancy, thus less capacity for user data. Such behavior is not optimal.
ECC code assignment with dependence on page reliability poses an implication Codeword size or Codeword Payload (AKA Payload) size changes from page to page. Such Code assignment technique can be called “Variable Code Rate”. This is in contrast, where all codes are equal, called “Fixed Code”.
Basic case of “Fixed Code” is “Nominal Code” which uses nominal amount of Bytes for user data and the rest for various Meta Data including ECC Meta Data. Nominal amount refers to the amount suggested by the specifications of the flash manufacturer.
A designer of system that includes a memory controller and a flash memory device may have several considerations in designing ECC codewords. Both reliability and performance considerations may be taken into account.
Once a code rate is set for a certain page it may contradict with other considerations such as a load imposed on the system in order to retrieve data segments as when a memory controller is requested to read a data segment (for example a 4 KB data segment), the memory controller must read all codewords that contain this data segment. I.e. round up to whole codewords. Even if only a small fraction of a data segment is contained by certain codeword. This causes transmission of more data over a link (or channel) between the flash memory device and the memory controller.
In some cases the amount of traffic may be twice the amount requested or even worse. This can cause performance degradation if the channel or ECC engine cannot support such traffic. It also causes power waste due to more channel and ECC engine operation.
FIG. 1 illustrates a prior art example of a relationship between codewords and data segments.
It is assumed that pages of the flash memory module are slightly longer than 16 KB and are designated to contain four data segments of 4 KB and codeword redundancies. Such configuration would be “Nominal Code”. 4 KB is the mostly used data unit due to computer operation systems' “page” based approach.
Once code rate is variable, pages with higher code rate contain more than 16 KB of user data, and pages with lower code rata contain less than 16 KB of data.
The first till twelfth codewords codeword_1—codeword_12 151-162 include redundancy 131-142 respectively.
First page (flash page) 101 is of a size of 16 KB+X, wherein X is the overall size of the redundancy of that page. The first page 101 stores first till fourth codewords codeword_1 codeword_4 151-154.
Each one of codeword_1-codeword_4 151-154 has a size of 4 KB+X/4. The first till fourth codewords includes first to fourth data segments (4 KB each) DS_1-DS_4 111-114 and redundancy 131-134.
The first till fourth codewords 151-154 are of a nominal code rate. The first till fourth data segments 111-114 are not split between codewords. Each one of these data segments can be retrieved by a single codeword transfer.
Second page (flash page) 102 is of a size of (16 KB+X), wherein X is the overall size of the redundancy of that page. The second page 102 includes fifth till eighth codewords codeword_5-codeword_8 155-158. These codewords include redundancy 135-138.
Each one of codeword_5-codeword_8 155-158 has a size of 4 KB+X/4, wherein the payload is 4.2 KB and the redundancy is X/4-0.2 KB.
Each one of codeword_5-codeword_8 155-158 includes portions of two data segments:                a. Codeword_5 155 includes portions of DS_5 115 and DS_6 116.        b. Codeword_6 156 includes portions of DS_6 116 and DS_7 117.        c. Codeword_7 158 includes portions of DS_7 117 and DS_8 118.        d. Codeword_8 155 includes portions of DS_8 118 and DS_9 119.        
The fifth till eighth codewords 155-158 are of a higher than nominal code rate. The fifth till ninth data segments 115-119 are split between codewords.
Third page (flash page) 103 is of a size of 16 KB+X, wherein X is the overall size of the redundancy of that page. The third page includes ninth till twelfth codewords codeword_9-codeword_12 159-162. These codewords include redundancy 139-142.
Each one of codeword_9-codeword_12 159-162 has a size of 4 KB+X/4, wherein the payload is 3.8 KB and the redundancy is X/4+0.2 KB.
Each one of codeword_9-codeword_11 159-161 includes portions of two data segments:                a. Codeword_9 159 includes portions of DS_9 119 and DS_10 120.        b. Codeword_10 160 includes portions of DS_10 120 and DS_11 121.        c. Codeword_11 161 includes portions of DS_11 121 and DS_12 122.                    Codeword_12 162 includes a portion of DS_12 122.                        
The ninth till twelfth codewords 159-162 are of a lower than nominal code rate. The ninth till twelfth data segments 119-122 are split between codewords. Each one of these data segments can be retrieved by a transferring pair of codewords.